The present invention relates to an electronic device and, in particular, to a flexible adhesive membrane and to an electronic device employing same.
There are many conventional ways of depositing solder or conductive adhesives for the bonding of electronic components and flip chip semiconductor devices to substrates, such as those set forth, for example in U.S. Pat. No. 3,401,126 entitled xe2x80x9cMethod of Rendering Noble Metal Conductive Composition Non-Wettable by Solderxe2x80x9d, U.S. Pat. No. 3,429,040 entitled xe2x80x9cMethod of Joining a Component to a Substratexe2x80x9d, U.S. Pat. No. 4,113,981 entitled xe2x80x9cElectrically Conductive Adhesive Connecting Arrays of Conductorsxe2x80x9d, U.S. Pat. No. 5,074,947 entitled xe2x80x9cFlip-Chip Technology Using Electrically Conductive Polymers and Dielectricsxe2x80x9d, U.S. Pat. No. 5,196,371 entitled xe2x80x9cFlip Chip Bonding Method Using Electrically Conductive Polymer Bumpsxe2x80x9d, U.S. Pat. No. 5,237,130 entitled xe2x80x9cFlip Chip Technology Using Electrically Conductive Polymers and Dielectricsxe2x80x9d, and U.S. Pat. No. 5,611,140 entitled xe2x80x9cMethod of Forming Electrically Conductive Polymer Interconnects on electrical Substratesxe2x80x9d. One problem common to these prior art techniques is that they all require operations that are substantially different from those normally associated with semiconductor fabrication. As a result, a substantially different kind of operation and process is being employed and a new business has evolved in which service companies perform solder deposition onto semiconductor wafers as well as adhesive deposition onto such wafers.
With the advancing usage of multi-chip module (MCM) packaging, knowledge of whether each individual semiconductor die is operative under the anticipated functional and stress conditions should be obtained before assembly of such dies into the MCM, so as to increase the yield of operative MCMs and to lower the cost thereof. This so-called known-good-die (KGD) testing is especially important for the large-volume production, such as is the case in the personal computer industry where many complex microprocessors, cache and other memory chips, and other electronic components, are assembled onto a large computer motherboard.
Conventionally, the stressing of semiconductor die (for burn in and electrical testing) is normally performed on an individual semiconductor die mounted in an individual test socket or carrier. The cost and time involved are substantial (see, Carter et al. xe2x80x9cKnown Good Die Comes of Agexe2x80x9d, Semiconductor International, October 1997). Besides the semiconductor die manufacturers, there are many companies now performing services as die processors. The cost of such processing could be reduced if die testing and stressing could be performed at the semiconductor wafer level. However, a suitable interface is required between the wafer and the test probes and other test equipment executing the testing protocol and under the test temperature environmental conditions.
This separation of these deposition, testing and other processing operations from the semiconductor wafer fabrication operations creates a time delay, perhaps as long as one to four weeks, in overall processing. This delay is unacceptable, especially where a problem arises because the delay in communicating the problem to the semiconductor wafer manufacturer delays the making of any required process change or improvement and usually results in wafers that are processed in the interim being unusable, further reducing the yield of acceptable product and increasing its cost.
Thus, there is a need for a fast and easy method of forming membranes of conductive adhesive and insulating adhesive underfill for attachment to electronic components, such as semiconductor flip chips, whether for the purpose of flip chip probing and stress testing, or for subsequent bonding to a substrate, or both.
In the case of solder deposition, solderable metallization must be first deposited on the contacts or bond pads which are usually aluminum, such as by an electroless, electrolytic, or vacuum evaporation process, so that the solder paste may be stenciled onto the solderable contacts or bond pads and reflowed to form solder bumps that will adhere to the contacts or bond pads. In the case of conductive adhesive, the contacts or bond pads are normally passivated with precious metal to prevent oxidation before the conductive adhesive in paste form is deposited, such as by screening or stenciling, onto the contacts or bond pads. The lowest cost for these processes is estimated to be about US$50 for a 6-inch diameter semiconductor wafer, even for high-volume production. While precious metal passivation must always be first made before any use of the conductive adhesive, the flash process for depositing nickel-gold or nickel-palladium combinations of layers is well established and can readily be accommodated in a sequential fabrication operation within almost any semiconductor fabrication facility.
Semiconductor die and other flip-chip components normally have fine contact pad size and pitch (i.e. center-to-center separation between adjacent contact pads or other features), whereas the substrate or xe2x80x9cnext-level boardxe2x80x9d to which they are bonded often employ lower-cost substrate materials such as FR4, ceramic, and other organic laminates, which in general afford electrical interconnections and contact pads that are normally on a larger scale and pitch than those afforded in semiconductor processing. For example, present-day semiconductor processing can produce micron-size and submicron-size features while the state-of-the-art etching techniques for FR4/copper and thick-film deposition on ceramic or organic substrates can produce features of about 75 microns or larger size. Thus, there is a need for making reliable and low cost interconnections without sacrificing the fine-feature size and fine pitch capabilities of semiconductor processing to accommodate lesser capabilities of the substrate processing operation.
Another consideration in attaching semiconductor and other flip-chip components to a substrate is that of obtaining and maintaining intimate interfacial contact between the component and the substrate so that there will be adequate thermal energy transfer which leads to lower temperature operation and to greater reliability. Good thermal conductivity will not be obtained where air, voids or other foreign matter is trapped between the chip and the substrate, and is particularly difficult to obtain where a patterned membrane of conductive and insulating organic polymer adhesive is employed. If a non-flowing dielectric underfill material is used, such as an epoxy of the sort described in U.S. Pat. No. 5,074,947 entitled xe2x80x9cFlip-Chip Technology Using Electrically Conductive Polymers and Dielectricsxe2x80x9d issued to Estes et al. voids will almost always form along the interface and thus, poor thermal conductivity will result across the interface between the electronic component and the substrate. In addition, if a rigid conductive adhesive of the sort described in the Estes et al. patent is used, the conductive adhesive will be subject to delamination and fracture under thermal stress and the interconnections formed thereby will be unreliable; the non-adhering dielectric underfill will not relieve the strain on the conductive adhesive and truly improve the aforementioned poor reliability.
A membrane having a pattern of conductive pads within an insulating matrix employing a high strength adhesive system having a high modulus of elasticity is reported by R. W. Johnson, et. al. xe2x80x9cAdhesive Based Flip Chip Technology for Assembly on Polyimide Flex Substratesxe2x80x9d, International Conference on Multichip Modules, (April, 1997). One problem with the approach reported by Johnson et. al. is that their rigid resin system having a high modulus of elasticity, such as a novolac epoxy base resin having a high glass transition temperature Tg of typically 150xc2x0 C. and a modulus of elasticity of about 2,000,000 psi, can not accommodate the substantial differences between the coefficients of thermal expansion (CTE) of semiconductor dies or chips and of substrate materials, such as FR4, ceramic and other common rigid substrate materials commonly employed, over the range of thermal temperatures typically specified and/or experienced. The approach of Johnson et al. to employ a flexible substrate that is capable of yielding or flexing may not be compatible with many applications, especially certain computer, telecommunication aerospace and defense applications. An alternate approach of engineering a customized substrate material that closely matches of the electronic components that will be attached thereto is both too expensive for many applications and impractical where the electronic components themselves have substantially different CTEs. In most applications, however, one must eventually connect to an FR4 printed circuit wiring board that has a very high CTE of about 17 ppm/xc2x0 C.
Thus, one major problem of component-to-substrate and component-to-circuit board interconnection is the internal stresses arising from the differing coefficients of thermal expansion between, for example, silicon chips and the next level substrate or board. Both conventional C4 rigid adhesive and solder-bump technologies are hampered by high stress-related failures when used over extreme temperature ranges and for semiconductor chips having larger dimensions. Although conventional rigid underfill helps to enhance the life of such interconnections under thermal cycling conditions, perhaps by a factor of 6-8 depending on size of the semiconductor die and the magnitude of the temperature excursions, the inherent problem of trading the beneficial compressive stress provided by the high-strength or rigid underfill that limits the thermal cycling strain with the oft devastating shear stress on the conductive interconnections that will delaminate or break the interconnection joints or the electronic components. Undesirably, every increase in the semiconductor die dimension or extension of the temperature range to a lower or higher temperature produces some increase in the shear stress, and thus reliability of the entire device must be reevaluated, such as by extensive and expensive testing.
Further, U.S. Pat. No. 5,667,884 entitled xe2x80x9cArea Bonding Conductive Adhesive Preformsxe2x80x9d issued to Bolger describes sheet preforms comprising a multiplicity of electrically conductive adhesive members, each being separated from the other by a non-electrically conductive adhesive, and being useful in the assembly of multi-chip modules and other electronic devices. The sheet preforms as described in the Bolger patent, however, remain on the release film on which they are formed until they are attached to a semiconductor component or a substrate, perhaps because they may lack dimensional stability if separated therefrom. In addition, Bolger""s sheet preforms also have several other undesirable, and perhaps more important, limitations. First, Bolger requires that the conductive adhesive elements extend above the surface of the non-conductive adhesive, generally having a height in the range of 125%-225%, and preferably about 150%-200%, of the thickness of the surrounding non-conductive adhesive, while also being less than 150% of its diameter (column 7, lines 8-15). Bolger further prefers that the conductive adhesive elements be conical in shape or be dome shaped to help prevent subsequently provided non-conductive adhesive from completely covering even one conductive adhesive member (column 6, lines 32-42). In fact, it appears from Bolger""s repetition of the point to be of great importance that care be taken to avoid covering the tops of previously formed conductive adhesive members with the non-conductive adhesive composition (column 12, lines 31-46).
Resins generally suitable according to Bolger include high Tg thermoplastic and thermosetting polymers that cure at greater than 120xc2x0 C. and have a glass transition temperature Tg greater than about 70xc2x0 C. (column 8, lines 33-46). Bolger further states that while reducing the glass transition temperature and the modulus of elasticity of the adhesive can reduce thermal stress, such may have major disadvantages, and so prefers a rigid (high Tg) adhesive to improve resistance to swelling, corrosion and other failure of adhesive bonds during exposure to heat and humidity (column 9, lines 38-56). High Tg materials are also preferred by Bolger to avoid excessive softening when the adhesive is exposed to high temperatures (Id.). The adhesive in Bolger""s examples I-III, for example, are novolac epoxy resins that form relatively rigid adhesives having a Tg which is typically over 150xc2x0 C. and a modulus of elasticity of over 106 psi, i.e. over one million psi (column 7, lines 46-55).
Accordingly, there is a need for a flexible membrane that avoids the tendency to interconnect failure inherent with rigid adhesives and yet is convenient to apply to components and substrates, i.e. is easy to utilize, and is easily fabricated. Further, there is a need for such flexible membranes that form reliable electrical connections even where the conductive adhesive members are covered by the non-conductive adhesive. It is desirable that electronic devices employing such flexible membranes be operable in environments including repetitive thermal cycling over a wide temperature range, including where the coefficients of thermal expansion of the electronic components and the substrates on which they are mounted differ substantially.
The present invention comprises a pattern of a plurality of electrically conductive features formed of a flexible electrically conductive adhesive having a predetermined flowability; and an electrically insulating matrix surrounding and adhering to the plurality of electrically conductive features, the electrically insulating matrix being a membrane formed of a flexible electrically insulating adhesive having a greater flowability than that of the flexible electrically conductive adhesive.
According to another aspect of the present invention, an electronic device comprises an electronic component having a pattern of electrical contacts on one surface thereof and a substrate having a pattern of electrical contacts on one surface thereof corresponding to the pattern of electrical contacts on the electronic component. A flexible adhesive membrane attaching the electronic component to the substrate comprises a plurality of electrically conductive features in a pattern corresponding to the pattern of electrical contacts and forming respective electrical connections between corresponding ones of the electrical contacts on the electronic component and on the substrate, the plurality of electrically conductive features formed of a flexible electrically conductive adhesive having a predetermined flowability. An electrically insulating matrix surrounds and adheres to the plurality of electrically conductive features, the electrically insulating matrix being a membrane formed of a flexible electrically insulating adhesive having a greater flowability than that of the flexible electrically conductive adhesive.
A method employing a flexible membrane to test flip-chip electronic components according to a further aspect of the invention comprises:
obtaining a flip-chip electronic component to be tested, the electronic component having a pattern of electrical contacts thereon;
obtaining a flexible membrane including a matrix of a flexible electrically insulating adhesive having a pattern of electrically conductive features therein formed of a flexible electrically conductive adhesive adhering to the flexible electrically insulating adhesive matrix, wherein the pattern of electrically conductive features of the flexible membrane corresponds to the pattern of electrical contacts on the electronic component;
applying the flexible membrane to the electronic component with ones of the pattern of electrical contacts electrically connecting to respective corresponding ones of the pattern of electrically conductive features;
obtaining a test apparatus having a plurality of electrical test probes connected thereto for testing electronic components;
connecting the electronic component to the test apparatus by touching selected ones of the test probes to selected ones of the electrically conductive features of the flexible membrane; and
operating the test apparatus to test the electronic component.